AMD has disabled the Loop Buffer functionality in its Zen 4 CPUs through a recent BIOS update (AGESA 1.2.0.2a). However, this change hasn't resulted in any performance degradation, as the existing Op Cache is sufficient for managing loops effectively.
The Loop Buffer, a feature exclusive to Zen 4, was designed to bypass the front-end pipeline for optimized performance. However, due to a lack of optimization and documentation, it didn't provide significant benefits. The Op Cache, a micro-op cache present in Zen architectures, already had enough bandwidth to handle the instructions intended for the Loop Buffer.
Discovery and Impact
The deactivation was first noticed by Chips and Cheese during testing of the Ryzen 9 7950X3D on an ASRock B650 PG Lightning motherboard. They observed that the Loop Buffer was active with the older BIOS 1.21 (AGESA 1.0.0.6) but inactive with BIOS 3.10 (AGESA 1.2.0.2a).
Loop Buffer vs. Op Cache
The Loop Buffer was intended to store instructions for loops (repeated sequences of code), reducing the need to fetch them from the cache or memory. However, the Op Cache already performs this function efficiently. This redundancy made the Loop Buffer's contribution negligible. AMD has omitted the Loop Buffer from its newer Zen 5 architecture.
Unlike Intel and Arm, which have successfully implemented similar features, AMD's Loop Buffer implementation wasn't optimized. The existing Op Cache mechanism continues to provide efficient instruction handling for Zen CPUs.
