A teardown of AMD's Ryzen 7 9800X3D processor, conducted by semiconductor analyst Tom Wassick, has revealed that a significant portion of the chip consists of dummy silicon. This structure is primarily for providing structural integrity to the chip.
3D V-Cache Stacking Explained
The Ryzen 9000 X3D processors stack the L3 SRAM cache chiplet below the heat-generating CCD (compute die). This configuration provides better thermal headroom and enables higher clock speeds. The CCD and 3D V-Cache chiplets are thinned to sub 10µm levels to expose the TSVs (Through-Silicon Vias) for hybrid bonding. Including the BEOL (Back-End of Line), the SRAM and CCD package measures 40-45µm thick.
The SRAM die is slightly larger (50µm) than the CCD on all sides. However, most of this additional area is expected to be empty. Excluding interconnects, the SRAM and CCD combined should be less than 20µm thick.
The Role of Dummy Silicon
To ensure the structural integrity of these thin components, AMD has added a substantial layer of dummy silicon both at the top and bottom of the stack. The entire chip package is about 800µm thick. When the 50µm die stack is subtracted, we get 750µm of dummy silicon — which represents **93% of the total stack**.
The various layers are connected through an oxide coating, which is thinner between the CCD and SRAM than between the dummy silicon and the dies for better thermal performance.
Further Investigation and Future AMD Plans
Tom Wassick plans to perform additional analysis with a Scanning Electron Microscope to address unanswered questions. Intel is not currently planning a direct response to AMD's 3D V-Cache technology, at least for the mainstream segment. AMD is expected to announce the 12-core and 16-core Ryzen 9 9900X3D and 9950X3D at CES next month.
