Broadcom has announced its groundbreaking 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, designed to significantly boost performance and efficiency in custom compute platforms for AI and high-performance computing (HPC).
High-Density Integration for AI at Scale
The 3.5D XDSiP integrates over 6000 mm² of silicon and up to 12 high-bandwidth memory (HBM) stacks into a single package. This innovative Face-to-Face (F2F) 3D stacking architecture directly connects the top metal layers of the dies, resulting in superior interconnect density, power efficiency, and reduced latency compared to traditional Face-to-Back (F2B) approaches.
This technology is crucial for meeting the immense computational demands of training large language models (LLMs), which require massive clusters of XPUs (custom accelerators). Traditional methods are struggling to keep pace, making advanced SiP integration essential.
Key Benefits of 3.5D XDSiP:
- 7x increase in signal density compared to F2B
- 10x reduction in die-to-die interface power consumption
- Minimized latency between compute, memory, and I/O
- Smaller and more cost-effective package size
Collaboration with TSMC
Broadcom's lead F2F 3.5D XPU integrates four compute dies, one I/O die, and six HBM modules, utilizing TSMC's advanced process nodes and 2.5D CoWoS packaging. This collaboration highlights the combined expertise of Broadcom in design and TSMC in advanced manufacturing.
"We look forward to productizing this platform to unleash AI innovations and enable future growth." - Dr. Kevin Zhang, TSMC.
Production and Availability
With over five 3.5D products currently under development, Broadcom's 3.5D XDSiP platform is gaining traction among its consumer AI customers. Production shipments are expected to begin in February 2026.
