At the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry revealed significant advancements in transistor and packaging technologies, designed to drive future semiconductor innovation.
Key Advancements
Intel highlighted several key breakthroughs:
Subtractive Ruthenium (Ru)
This new material aims to improve chip interconnections, reducing line-to-line capacitance by up to 25% at pitches of 25nm or less. It's a cost-effective solution potentially replacing copper damascene in future nodes.
Selective Layer Transfer (SLT)
SLT is a heterogeneous integration solution that boosts chip-to-chip assembly throughput by up to 100x. This enables smaller, more flexible chiplets for increased functional density and cost efficiency, particularly beneficial for AI applications.
Silicon RibbonFET CMOS
Intel showcased 6nm gate length silicon RibbonFET CMOS transistors with superior performance and reduced short-channel effects, furthering gate length scaling and supporting Moore's Law.
Gate Oxide for Scaled GAA 2D FETs
Research into gate oxide modules for scaled GAA 2D FETs explores the potential of 2D materials, like transition metal dichalcogenides (TMDs), as future silicon replacements in advanced transistors.
300mm Gallium Nitride (GaN) Technology
Intel is advancing its 300mm GaN technology, offering higher performance, voltage, and temperature capabilities than silicon, particularly beneficial for power and radio frequency (RF) electronics.
Vision for the Future
Intel Foundry also presented its vision for future advanced packaging and transistor scaling, focusing on:
- Advanced memory integration
- Hybrid bonding for bandwidth optimization
- Modular system expansion with enhanced connectivity
The company also emphasized the need for ultra-low voltage transistors (below 300 millivolts) to address thermal bottlenecks and improve energy efficiency.
